Hardware-Conscious Data Processing (ST 2022) - tele-TASK

By Prof. Dr. Tilmann Rabl

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Episodes: 19

Description

Hardware development continuously advances, with different technologies improving at different pace. While the amount of transistors in a CPU package are growing, the single core performance is stagnating due to physical limitations. These trends require changes in data processing to keep database management systems efficient. In this lecture, we will take a look at current computer architectures and accelerator technologies and how they can be used for efficient data processing. We will cover CPU and memory architecture; the storage hierarchy; modern memory technolgoies, such as NVM and NVMe; fast interconnects, such as Infiniband, RDMA, and NVLink; and accelerators, such as GPUs and FPGAs. The course has a significant practical part, where the students learn to implement data structures and algorithms tailored to hardware concious data processing.

Episode Date
Query Compilation for Modern, Heterogenous Processors
Jul 26, 2022
Efficient Answering of Historical What-if Queries
Jul 20, 2022
Field Programmable Gate Arrays
Jul 19, 2022
Data Processing on GPUs II
Jul 12, 2022
Data Processing on GPUs
Jul 05, 2022
Networking
Jun 28, 2022
Storage
Jun 21, 2022
Persistent Memory
Jun 14, 2022
Query Execution Models
Jun 08, 2022
Data Structures
May 31, 2022
Multicore Parallelism & Non-Uniform Memory Access
May 24, 2022
Multicore Parallelism
May 17, 2022
SIMD & Task 1: SIMD Scan
May 10, 2022
CPU - Instruction Execution & SIMD
May 05, 2022
CPU - Instruction Execution
May 03, 2022
CPU and Caching
Apr 28, 2022
Performance Management & Benchmarking
Apr 26, 2022
DBMS Recap
Apr 21, 2022
Introduction
Apr 21, 2022