Hardware-Conscious Data Processing (ST 2023) - tele-TASK

By Prof. Dr. Tilmann Rabl

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Episodes: 25

Description

Hardware development continuously advances, with different technologies improving at different pace. While the amount of transistors in a CPU package are growing, the single core performance is stagnating due to physical limitations. These trends require changes in data processing to keep database management systems efficient. In this lecture, we will take a look at current computer architectures and accelerator technologies and how they can be used for efficient data processing. We will cover CPU and memory architecture; the storage hierarchy; modern memory technolgoies, such as NVM and NVMe; fast interconnects, such as Infiniband, RDMA, and NVLink; and accelerators, such as GPUs and FPGAs. The course has a significant practical part, where the students learn to implement data structures and algorithms tailored to hardware concious data processing.

Episode Date
Compute Express Link
Jul 25, 2023
Summary
Jul 20, 2023
Field Programmable Gate Arrays (2)
Jul 12, 2023
Field Programmable Gate Arrays
Jul 11, 2023
Data Processing on GPUs II
Jul 05, 2023
Data Processing on GPUs
Jul 04, 2023
Storage & Networking
Jun 28, 2023
Storage
Jun 27, 2023
Persistent Memory
Jun 20, 2023
Non-uniform Memory Access
Jun 14, 2023
Concurrency and Synchronization
Jun 13, 2023
Multicore Parallelism (2)
Jun 07, 2023
Multicore Parallelism
May 31, 2023
Profiling
May 24, 2023
Data Structures
May 23, 2023
Query Execution Models
May 17, 2023
Vectorized Execution (2)
May 16, 2023
Task 1: SIMD Delta Scan
May 10, 2023
Vectorized Execution
May 09, 2023
CPU and Caching & Instruction Execution
May 03, 2023
CPU and Caching (2)
May 02, 2023
CPU and Caching
Apr 26, 2023
Performance Management & Benchmarking
Apr 25, 2023
DBMS Recap
Apr 19, 2023
Introduction
Apr 18, 2023